1. Field of the Invention
The present invention relates to a semiconductor memory device which uses a self-timed method.
2. Description of the Related Art
A semiconductor memory device that uses a self-timed method to determine the timing of an internal control signal is known. In such a memory device, the timing of the internal control signal is determined based on a signal which has passed through a signal path including a read-out circuit, dummy memory cells and a selection circuit having a load equivalent to that of a read-out operation of usual memory cells.
In the self-timed method, the timing of the internal control signal is determined by canceling the variations of the characteristics of the memory cells in the semiconductor memory device due to the process variations by using the signal passing the corresponding dummy cell.
The self-timed method is used to determine the timing of various internal control signals, such as the word line select signal, the sense amplifier activation signal (in a case of the semiconductor memory device with the sense amplifier), and the data latch activation signal (in a case of the semiconductor memory device without the sense amplifier).
In the following, a description will be given of a conventional method of determining the timing of the data latch activation signal in the case of the semiconductor memory device having no sense amplifier (e.g., SRAM) as an example. However, the same method is applicable for the sense amplifier activation signal or the other signals, as well as the data latch activation signal.
FIG. 1 shows an example composition of a conventional semiconductor memory device for generating an internal control signal. FIG. 2 is a timing chart for explaining the method of determining the timing of the internal control signal in the conventional semiconductor memory device of FIG. 1.
As shown in FIG. 1, the semiconductor memory device 10 includes a dummy cell array 11, a memory cell array 12, a decoder 13, an I/O (input/output) latch circuit 14, and a timing control circuit 15. For example, the semiconductor memory device 10 is an SRAM having no sense amplifier, which uses the conventional self-timed method.
In the semiconductor memory device 10 of FIG. 1, the dummy cell array 11 is disposed with the memory cell array 12 at the location farthest from the decoder 13. In this case, the timing of the data latch activation signal is determined as follows.
As indicated by the arrow in FIG. 1, the timing control circuit 15 determines the timing of the data latch activation signal, which is inputted to a corresponding output latch portion of the I/O latch circuit 14, based on a signal which has passed a dummy bit line through a corresponding dummy cell of the dummy cell array 11 connected to the word line selected by the decoder 13. In the corresponding output latch portion, the data of the corresponding memory cell in the memory cell array 12 is read out in response to the determined activation timing.
In FIG. 2, (1) indicates the state of the clock signal “CK” outputted to each circuit of the semiconductor memory device 10, (2) indicates the state of the selected word line signal “WL”, (3) indicates the state of the signal “stf” passing the dummy bit line through the corresponding dummy cell, and (4) indicates the state of the data latch activation signal “OUTPUT LATCH ENABLE” inputted to the corresponding output latch portion.
In this case, as shown in FIG. 2, the timing of the data latch activation signal (the rising edge of OUTPUT LATCH ENABLE) is determined by the rising edge of the signal “stf” from the corresponding dummy cell. Moreover, the timing of the data latch deactivation signal (the falling edge of OUTPUT LATCH ENABLE) is preset to an instant after a fixed time internal from the timing of the data latch activation signal according to the time delay of a set of inverters provided in the dummy bit line.
FIG. 3 shows another example composition of a conventional semiconductor memory device for generating an internal control signal.
As shown in FIG. 3, the semiconductor memory device 10A includes a dummy cell array 11A, the memory cell array 12, the decoder 13, the I/O latch circuit 14, and a timing control circuit 15A. For example, the semiconductor memory device 10A is an SRAM having no sense amplifier, which uses the conventional self-timed method.
In the semiconductor memory device 10A of FIG. 3, the dummy cell array 11A is disposed with the memory cell array 12 at the location nearest to the decoder 13. In this case, the timing of the data latch activation signal is determined as follows.
As indicated by the arrow in FIG. 3, the timing control circuit 15A determines the timing of the data latch activation signal, which is inputted to a corresponding output latch portion of the I/O latch circuit 14, based on a signal which has passed a dummy bit line through a corresponding dummy cell of the dummy cell array 11A connected to the word line selected by the decoder 13. In the corresponding output latch portion, the data reading of the corresponding memory cell in the memory cell array 12 is started in response to the determined activation timing.
In this case, the timing of the data latch activation signal is determined by the rising edge of the signal “stf” from the corresponding dummy cell, similar to the example of FIG. 1. Moreover, the timing of the data latch deactivation signal is preset to an instant after a fixed time interval from the timing of the data latch activation signal according to the,time delay of a set of inverters provided in the dummy bit line.
In addition, Japanese Laid-Open Patent Application No. 11-203873 discloses a semiconductor memory device in which changes in the amplitude of a data line at the time of reading operation are simulated by using dummy memory cells in order to generate an internal control signal. Japanese Laid-Open Patent Application No. 11-96768 discloses a semiconductor memory device in which a data read-out signal is output to a sense amplifier after a word line select signal is received.
In the example of FIG. 1, the corresponding dummy cell is disposed with the memory cell array 12 at the location farthest from the decoder 13, and the time the output signal of the corresponding dummy cell reaches the timing control circuit 15 is longer than the time the output signals of all the memory cells on the selected word line in the memory cell array 4 reach the timing control circuit 7. Therefore, the timing margin needed for the timing determination of the data latch activation signal is adequate.
However, the determined timing of the data latch activation signal may have an excessively large amount of the timing margin because the signal is delivered through the signal path indicated by the arrow in FIG. 1.
In the example of FIG. 3, the corresponding dummy cell is disposed with the memory cell array 12 at the location nearest to the decoder 13, and the timing of the data latch activation signal can be set to the minimum time for reading the data from the memory cell array 12.
Hence, in the example of FIG. 3, high-speed data reading is possible. However, it cannot be said that the signal path of the dummy cell array 11A in the example of FIG. 3 correctly simulates the selection signal path of the actual memory cells. The timing of the data latch deactivation signal is preset to an instant after a fixed time interval from the timing of the data latch activation signal according to the time delay of a set of inverters provided in the dummy bit line, and, when the variations of the logic circuits do not accord with the variations of the characteristics of the memory cells, the timing margin needed for the timing determination of the data latch activation signal is likely to be inadequate.
The timing margin for the timing determination of the internal control signal in the example of FIG. 1 is adequately large, but the example of FIG. 1 is not suitable to attain high-speed data reading. Moreover, in the example of FIG. 3, high-speed data reading is possible but there is the possibility that the timing margin would be inadequate.